Semiconductor memory device and operating method for a semiconductor memory device

ABSTRACT

A magnetoresistive semiconductor memory device is proposed, in which a magnetic field can be applied to memory cells by means of a magnetic field applying device such that a desired magnetization can be impressed on hard-magnetic layers of the memory cells acted on.

BACKGROUND

The invention relates to a semiconductor memory device and to a methodfor operating a semiconductor memory device.

In semiconductor memory devices based on a magnetoresistive storagemechanism, in particular in MRAM memories, what is crucially importantis a prescribed and fixed premagnetization of specific regions of thememory cells in comparison with freely magnetizable regions of therespective memory cells. In this case, a tunneling resistance whichforms between two magnetized layers and is used to measure an electriccurrent for sensing the memory content of a respective cell depends verygreatly on the strength and the orientation of the fixedly prescribedpremagnetization and also on the freely adjustable magnetization.

Although there are known materials in the construction of memory cellsbased on magnetoresistive storage effects in which a fixedly presetpremagnetization hardly changes with respect to time, it cannot beensured that a memory area will exhibit 100% freedom from faults overthe period of utilization of a number of years on account of the highnumber of individual memory cells in a memory area for semiconductormemory devices based on magnetoresistive storage mechanisms.

Thus, it is conceivable, for example, that due to external interferencefields, due to thermal influences and/or also spontaneously, specificpremagnetized regions of the memory cells will exhibit deviations from adesired magnetization with regard to the strength and/or the orientationof the premagnetization, with the result that individual memory cells ormemory elements of a memory area may become unusable. A term that isalso used in this connection is so-called magnetic creeping, in which amisorientation of the premagnetization or else a decrease in thestrength of the premagnetization is a temporally crawling process, inwhich case a malfunction of the respective memory cell can then suddenlyoccur.

SUMMARY

One embodiment of the invention specifies a semiconductor memory devicebased on a magnetoresistive storage mechanism and also a method foroperating a semiconductor memory device based on a magnetoresistivestorage mechanism, in the case of which a memory operation that is asreliable as possible can be realized over a long operating period.

One embodiment of the invention is a semiconductor memory device basedon a magnetoresistive storage mechanism, and in particular the MRAMmemory, have at least one memory area, which, for its part, has aplurality of memory cells. Furthermore, at least one magnetic fieldapplying device is provided, by means of which a common and at leastlocally homogeneous magnetic field can be applied to at least some ofthe memory cells in a controllable and/or defined fashion such that, asa result, at least parts or regions of the memory cells acted on can beamplified and/or oriented in defined and/or controllable fashion withregard to their magnetization (magnetic polarization).

In one case of a magnetoresistive semiconductor memory device inaccordance with the present invention, a magnetic field applying deviceis formed by means of which, during operation, a magnetic field can beapplied to the memory cells controllably in a defined manner in orderthereby to amplify and/or orient the magnetic polarization and/or themagnetization of the individual cells in a defined manner andcontrollably. Thus, during operation, magnetic creeping can becounteracted by virtue of the fact that, for the respective componentparts of the memory cells which are to be formed with a fixedpremagnetization, this premagnetization is formed and/or amplified in awell-defined manner. As a result, a misorientation of thepremagnetization of the respective memory cells is counteracted and itis thus possible to speak in this case of a reorientation oramplification of the premagnetization.

In one embodiment of the semiconductor memory device according to theinvention, it is provided that the magnetic field applying device isformed entirely or partially in a housing device provided for thesemiconductor memory device. In this case, the specific housingcomponent parts of the housing device or else the housing device as awhole can be formed as a prefabricated element with the magnetic fieldapplying device, without having to modify the production and testprocedure for the semiconductor memory device in the narrower sense,that is to say of the semiconductor module underlying the semiconductormemory device. Consequently, the semiconductor memory underlying thesemiconductor memory device can be formed and tested independently ofthe magnetic field applying device to be provided.

In another embodiment of the semiconductor memory device according tothe invention, it is provided that the magnetic field applying device isformed as a coil arrangement. The latter may have one coil or aplurality of coils.

In this case, the coil arrangement is arranged and/or formed in such away that a magnetic field of the inner region of at least one coil canbe applied to at least some of the memory cells. On account of thegeometry of coils, it is precisely the inner regions that haveparticularly high magnetic field strengths during operation, aparticularly suitable homogeneity of the magnetic field generated alsobeing ensured.

In order to realize the procedure, it is provided that at least one coilof the coil arrangement spatially encloses at least some of the memorycells.

This may mean, for example, that the semiconductor module underlying thesemiconductor memory device is formed and/or arranged at least partly inthe inner region of at least one coil of the coil arrangement.

Certain spatial regions in coils of coil arrangements can generate, inthe outer region, suitable magnetic field strengths with a suitableorientation.

Therefore, in accordance with another embodiment of the semiconductormemory device according to the invention, it is provided that a magneticfield of the outer region of at least one coil can be applied to atleast some of the memory cells.

To that end, it is provided that at least part of the semiconductormodule underlying the semiconductor memory device is arranged and/orformed in the outer region of at least one coil.

The semiconductor memory device according to an embodiment of theinvention have favorable properties with regard to a reorientationand/or amplification to be carried out for the premagnetization providedresult if two coils are provided as elements of the coil arrangement ofthe magnetic field applying device.

If a plurality of coils, either two or more, are provided in theformation of the coil arrangement of the magnetic field applying device,then said coils are formed in identically acting or identical fashion.

Particularly simple field conditions result if, in accordance with analternative embodiment of the semiconductor memory device according tothe invention, the plurality of coils, in particular two coils, of thecoil arrangement of the magnetic field applying device are formed inaxially symmetrical fashion with respective axes of symmetry and if, inthis case, the two or more coils additionally run with their axes ofsymmetry on a common axis and/or are arranged collinearly with respectto one another.

In this case, it is furthermore advantageous if the two coils arearranged and/or formed along their common axes or axis of symmetry in amanner spaced apart spatially from one another with an intermediateregion, in which case the semiconductor module underlying thesemiconductor memory device is then arranged and/or formed at leastpartly in said intermediate region between the coils, in particular inthe vicinity of the common axis or axis of symmetry of the coils. Thisprocedure is advantageous insofar as the geometrical arrangement of thecoils thus formed enables, during operation, a particularly high fieldstrength and, at the same time, a particularly high homogeneity in theintermediate region between the coils that are operated serially withrespect to one another.

The memory cells each have or form a magnetoresistive memory element, inparticular a TMR stack element with at least one hard-magnetic layer.

Furthermore, it is provided that the memory cells each have at least onesoft-magnetic layer as memory layer and also a tunnel layer arrangedbetween the hard-magnetic layer and the soft-magnetic layer.

Furthermore, in one embodiment it is advantageous that the hard-magneticlayer is in each case formed with a predefined and fixed magnetizationas desired magnetization, said desired magnetization being oriented, inparticular, in each case perpendicularly to a course direction of theTMR stack elements, that is to say the direction of the course of thesequence of layers of the TMR stack elements, for example in the planeof the layers.

The semiconductor memory device according to one embodiment of theinvention is configured in a particularly simple manner if the pluralityof memory cells is formed essentially in identically acting or identicalfashion.

Furthermore, in one embodiment it is advantageous that the plurality ofmemory cells is arranged and/or formed in such a way that theirmagnetizations are oriented essentially identically and/or lieessentially in a common plane.

One embodiment of the present invention provides a method for operatinga semiconductor memory device based on a magnetoresistive storagemechanism, and in particular for an MRAM memory. The operating methodaccording to this embodiment of the invention has a step of read-out andexternal storage of memory contents of each memory cell of a memory areaof the semiconductor memory device. Afterward, a magnetic field is thenapplied to the semiconductor memory device and, in the process, amagnetic field is applied to at least some of the memory cells in orderto impress a magnetization on hard-magnetic layers of the memory cellsin a definable and/or controllable fashion. Afterward, the externallystored memory contents are then written back to each cell of the memoryarea.

Thus, this embodiment of the method firstly saves the data contents ofthe memory area in order subsequently to amplify and/or reorient thehard-magnetic layers of the memory cells by impressing a magnetizationin a definable and/or controllable manner. Afterward, the informationstate of the memory area is then re-established by writing back theexternally stored or saved memory contents to respective memory cells.

The operating method according to one embodiment of the invention isconfigured in a particularly advantageous manner if the magnetic fieldis set in a controlled fashion in terms of strength, orientation andtime duration in such a way that each of the memory cells to be acted onhas impressed on it a magnetization in a defined fashion in terms ofstrength and orientation so that a reliable memory operation is ensured,and/or that, in particular, the respective magnetization ofhard-magnetic layers of the memory cells can be reoriented toward thedesired magnetization and/or amplified.

Furthermore, in one embodiment the steps—underlying the operatingmethod—of externally saving the memory contents, of applying a magneticfield for reorientation and/or for amplification of the magnetization,and of writing back the externally saved memory contents are carried outrepeatedly at time intervals, in particular at a time interval of oneyear or less. This repetition can be effected regularly.

A regularity in the execution of the operating method thus ensures apreventive measure. On the other hand, the execution of the method canalso be carried out by an explicit request by a user or by a using unit,for example for the case where an error state is ascertained with regardto the storage or read-out of information contents.

The tunneling magnetoresistance memory elements, TMR, also calledmagnetic tunneling junctions MTJ, of magnetic random access memories(MRAMs) have a passive and an active ferromagnetic layer. Themagnetization of the active layer is rotated during writing anddestructive reading relative to the fixed direction of magnetization ofthe passive magnetic layer, parallel or antiparallel to said directionof magnetization.

The nonvolatility of this type of memory is essentially concomitantlydetermined by the orientation of the magnetization of the passivehard-magnetic layer, said orientation not changing with respect to time.The orientation of this magnetization is defined once during theproduction process. The deviation that can be tolerated in this case islow, less than one degree. This narrow distribution of the magnetizationaround a predetermined direction can become wider over the course oftime with and without external magnetic interference fields, for exampledue to magnetic creeping. The changes in magnetization must be expectedto take place inhomogeneously, proceeding from nucleation centers. As aresult, individual memory elements may become unusable, and/or theirmemory contents may be lost.

The time scale to which the nonvolatility of MRAM memories based on thetunneling magnetoresistance effect (TMR) relates is not known. It mustbe expected, however, that, due to thermal activation of the magneticcreeping in the hard-magnetic layer, this time scale will fall withinthe range of the period of utilization of the memories of a few years.

It is not known how the limitation of the nonvolatility caused bymagnetic creeping can be prevented.

Changes in magnetization due to external magnetic interference fieldsand the loss of stored information thus caused can be prevented bymagnetic shielding with materials of high permeability.

These are ineffective, however, with regard to the information lossescaused by magnetic creeping.

The hard-magnetic layer can be reoriented by an external magnetic field,even during the operation of an MRAM module. Therefore, one embodimentof the invention provides for the repair or the preventive refreshing ofmemory cells which have lost their functionality due to a change in themagnetization of the hard-magnetic layer.

For this purpose, firstly the content of the memory module isbuffer-stored in another arbitrary medium. A magnetic field large enoughto reorient the hard-magnetic layer is then applied, for example bymeans of a coil suitably integrated in the package, or a pair of coils.Afterward, the former content can be transferred back into the modulefrom the buffer memory. This operation can be repeated as often asdesired.

If, as proposed, a coil or a pair of coils is integrated into thepackage of the module, then the orientation of the magnetization of thehard-magnetic layer of the module can be refreshed in situ. Acorresponding logic with driving can carry out this operationautomatically at predetermined time intervals. The time scale thuschanges for the definition or requirements with regard to nonvolatilitymade of the hard-magnetic layer. It is possible to realize long-termnonvolatile memories even with hard-magnetic layers whose magneticorientation decomposes over a shorter time scale.

Hard-magnetic layers can be obtained through special alloys offerromagnetic and nonferromagnetic elements, for example CoFe, CoCr,CoPt, CoCrFe.

However, the magnetic switching thresholds of ferromagnetic layers canalso be increased through the choice of layer geometry (shape,thickness) in comparison with the soft-magnetic layers.

A further possibility consists in making ferromagnetic layers “harder”by coupling to underlying, alternatively overlying, antiferromagneticlayers (for example made of IrMn, PtMn).

Appropriate ferromagnetic layers are generally layers which contain atleast one of the elements Fe, Ni, Co, Cr, Mn, Gd, Dy or Bi or comprisealloys thereof.

One embodiment of the invention includes exploiting the insight that, incontrast to other nonvolatile memories, such as flash memories, forexample, defective cells or bits can be refreshed or repaired by anapplied external field.

The magnetic field of the hard-magnetic layer can be refreshed orrepaired contactlessly by exposing the chip in the package to anoriented magnetic field.

If a corresponding coil or a pair of coils is integrated into thepackage, for example a housing, then memory cells whose defect isattributable to a misorientation of the magnetization in thehard-magnetic layer can be repaired in situ in the course of operation,for example during times in which the corresponding memory cells are notaccessed.

If this reorientation is carried out as a preventive measure, then thenonvolatility of these memory elements can be improved.

The magnetic field for re-establishing the direction of magnetization ofthe hard-magnetic layer is generated for example by a pair of coilsmounted together with the MRAM chip in a chip housing. The magneticfields of the two series-connected coils are unidirectional and focusedonto the chip plane.

It is also possible to use an elongate magnetic coil mounted above thechip in a housing. For reorientation of the hard-magnetic layer, theexternal magnetic field which is approximately parallel to the coil axisis used, for example, which magnetic field, together with the magneticfield within the coil, forms a closed magnetic field arrangement.Compared with the above procedure, the simplicity of the mounting isadvantageous, but the lower magnetic-field-to-current efficiency isdisadvantageous.

The following further exemplary embodiments are conceivable:

-   -   the magnetic coil encloses the MRAM chip in closely adjoining        fashion and comprises one or more coil segments. In this case,        the homogeneous magnetic field is advantageous; the magnetic        field is at a maximum for a given current. The complicated        mounting is disadvantageous.    -   the magnetic coil is integrated into the constituent parts of        the housing in such a way that a complete magnetic coil        enclosing the MRAM chip is produced after the mounting of the        MRAM chip and assembly of the constituent parts of the housing.        The simple mounting and the high magnetic-field-to-current        efficiency are advantageous in this case. The expensive, complex        housing is disadvantageous.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description.

The elements of the drawings are not necessarily to scale relative toeach other.

Like reference numerals designate corresponding similar parts.

FIGS. 1A-D diagrammatically illustrate four different intermediatestates of a memory cell which are attained in accordance with oneembodiment of the operating method according to the invention.

FIGS. 2A-C illustrate three different embodiments of the semiconductormemory device according to the invention in sectional side view.

FIG. 3 illustrates another embodiment of the semiconductor memory deviceaccording to the invention in partial sectional and perspective sideview.

FIG. 4 illustrates a further embodiment of the semiconductor memorydevice according to the invention in partially sectional side view.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

The procedure in accordance with one embodiment of the operating methodaccording to the invention is explained in detail on the basis of asingle memory cell 30 based on a magnetoresistive storage mechanism withreference to FIGS. 1A to 1D in sectional side view.

In the embodiment of the invention illustrated in FIGS. 1A to 1D, amagnetoresistive memory cell 30 comprises a hard-magnetic layer 31 h, asoft-magnetic layer 31 w and a tunnel layer 31 t provided in between.During the fabrication of a semiconductor memory device according to oneembodiment of the invention, which has a plurality of the memory cells30 illustrated in FIGS. 1A to 1D in a memory area 20, a magnetization Mis impressed on the hard-magnetic layer 31 h of each memory cell 30,which magnetization is essentially identical to a desired magnetizationMdesired:M=Mdesired, to be precise in terms of magnitude and direction.

By means of corresponding write operations, an information magnetizationor storage magnetization Msp can be impressed on the soft- magneticlayer 31 w, which serves as memory layer, parallel or antiparallel tothe desired magnetization Mdesired of the, hard-magnetic layer 31 h. Acomparatively high or a comparatively low electrical tunnelingresistance via the tunnel layer 31 t of the memory cell 30 isestablished depending on whether the storage magnetization Msp of thesoft-magnetic layer 31 w is oriented parallel or antiparallel to thedesired magnetization Mdesired of the hard-magnetic layer 31 h.

This state is illustrated in FIG. 1A and is present at an instant t=0and for some time afterwards, the storage magnetization Msp of thesoft-magnetic layer 31 w being indicated in dotted fashion on account ofits variability.

As time passes, the probability of the magnetization M of thehard-magnetic layer 31 h deviating from the desired magnetizationMdesired increases. This applies both with regard to the absolutemagnitude of the magnetization M and with regard to the direction of themagnetization M in comparison with the desired magnetization Mdesired.FIG. 1B diagrammatically illustrates that, for a time t above a criticaltime Tcrit, not specified in any further detail, there is a deviation ofthe magnetization M of the hard-magnetic layer 31 h in terms ofmagnitude and direction in comparison with the desired magnetizationMdesired:M≠Mdesired.

In the text above and below, M, Msp, Mdesired always representfixed-amount quantities or quantities that are averaged over thecorresponding layers.

Such a deviation can have the effect that the functional reliability isno longer ensured when writing and/or reading information contents toand/or from the soft-magnetic layer 31 w of the memory cell 30.

Accordingly, an external magnetic field H with respect to the memoryelement 30 (or the memory cell 30) is applied in accordance with theillustration of FIG. 1C. This external magnetic field H is chosen withregard to its direction and its magnitude such that the magnetization Mof the hard-magnetic layer 31 h is again oriented in accordance with thedesired magnetization Mdesired and, in its magnitude, assumes acorresponding or higher value, as is illustrated in FIG. 1C.

After the external magnetic field H with respect to the memory cell 30has been switched off, an amplified and reoriented magnetization Mcorresponding to the desired magnetization Mdesired:M=Mdesired remainsin the hard-magnetic layer 31 h.

This is illustrated in FIG. 1D, in which case, in the transition fromthe state of FIG. 1B to FIG. 1C, the information stored in thesoft-magnetic layer 31 w is read from the memory cell 30 and issubsequently written back to the soft-magnetic layer 31 w in thetransition from the state of FIG. 1C to the state of FIG. 1D, so thatthe storage magnetizations Msp of the states of FIGS. 1B and 1Dessentially correspond.

FIGS. 2A to 2C illustrate three embodiments of the semiconductor memorydevice 10 according to the invention in diagrammatic and sectional sideview.

In FIGS. 2A to 2C, the semiconductor memory device 10 according to oneembodiment of the invention has a memory area 20 which, for its part,has a plurality of memory elements or memory cells 30 which, for theirpart, have the structure illustrated in FIGS. 1A to 1D, for example. Thememory area 20 in each case has the structure of a semiconductor module20 or of a chip 20.

The magnetic field applying devices 40 of the embodiments of FIGS. 2A to2C are formed by coil arrangements 40. In this case, one coil 41 isprovided in each of the embodiments of FIGS. 2A and 2B and two coils 41and 42 are provided in the embodiment of FIG. 2C. In each case only thecross sections of the turns 41 w and 42 w, respectively, of the coils41, 42 are indicated.

In the embodiments of FIGS. 2A to 2C, all the coils have a cylindricalor parallelepipedal configuration with in each case a centrally arrangedaxis 41 x and 42 x of symmetry.

In the embodiment of FIG. 2A, the memory chip or memory area 20 with itsmemory cells 30 is arranged in the inner region 41 i of the coil 41 ofthe coil arrangement or magnetic field applying device 40 and hasapplied to it there during operation a homogeneous magnetic field Hi,which, in terms of direction and magnitude, generates precisely thedesired magnetization Mdesired in the hard-magnetic layers 31 h of thememory cells 30.

In the embodiment of FIG. 2B, the memory area 20 with its memory cells30 is provided in the outer region 41 a of the coil 41 of the coilarrangement 40 or magnetic field applying device 40, so that the outerfield Ha of the coil 41 is exclusively used there for the applicationand reorientation.

In the embodiment of FIG. 2C, the memory area 20 with its memory cells30 is situated in the intermediate region Z of the first coil 41 and thesecond coil 42, which are of identical design and have axes 41 x and 42x of symmetry, said axes 41 x and 42 x of symmetry lying and beingoriented on a common axis X of symmetry. Consequently, in the embodimentof FIG. 2C, the combined emergence field Ha of the first coil 41 andsecond coil 42 is used as superposed magnetic field for thereorientation of the magnetization M of the hard-magnetic layers 31 h.

FIG. 3 illustrates, in diagrammatic, partially perspective sectionalside view, a more highly concretized embodiment of a semiconductormemory device 10 according to the invention using the arrangementillustrated in FIG. 2C. First and second coils 41, 42 are providedthere, too. Said coils are constructed essentially identically and haveaxes 41 x, 42 x of symmetry arranged collinearly on a line. The firstand second coils 41, 42 are spaced apart spatially from one another byan intermediate region Z. Located in the intermediate region Z is thechip as memory area 20 with the memory cells 30 provided therein. Theillustration also shows a carrier substrate 60 and external terminals70. The first and second coils 41 and 42 are provided here as structuresthat are integrated into a housing that is not concretized in anyfurther detail here.

FIG. 4 illustrates a more highly concretized embodiment of thearrangement of FIG. 2B in sectional side view. A magnetic field applyingdevice 40 with a coil arrangement 40 comprising a single coil 41 isprovided there in the housing region 50. The memory area 20 formed as achip is situated in the outer region 41 a of the individual coil 41. Thechip or memory area 20 and all further components lie on a carriersubstrate 60 and are contact-connected externally by external terminals70.

1-20. (canceled)
 21. A semiconductor memory device based on amagnetoresistive storage mechanism, comprising: at least one memory areahaving a plurality of memory cells; and at least one magnetic fieldapplying device, by means of which a common and at least locallyhomogeneous magnetic field can be applied to at least some of the memorycells in a controllable fashion; wherein at least regions of the memorycells acted on by the magnetic field applying device can be amplifiedand oriented in a controllable fashion with regard to theirmagnetization.
 22. The semiconductor memory device of claim 21, whereinthe magnetic field applying device is formed at least partially in ahousing device provided for the semiconductor memory device.
 23. Thesemiconductor memory device of claim 21, wherein the magnetic fieldapplying device is formed as a coil arrangement, having at least onecoil.
 24. The semiconductor memory device of claim 23, wherein the coilarrangement is arranged such that a magnetic field of an inner region ofat least one coil can be applied to at least some of the memory cells.25. The semiconductor memory device of claim 23, wherein at least onecoil spatially encloses at least some of the memory cells.
 26. Thesemiconductor memory device of claim 24, wherein a semiconductor moduleunderlying the semiconductor memory device is formed at least partly inthe inner region of at least one coil.
 27. The semiconductor memorydevice of claim 26, wherein a magnetic field of an outer region of atleast one coil can be applied to at least some of the memory cells. 28.The semiconductor memory device of claim 27, wherein at least part ofthe semiconductor module underlying the semiconductor memory device isarranged in the outer region of at least one coil.
 29. The semiconductormemory device of claims 23, wherein two coils are provided.
 30. Thesemiconductor memory device of claims 23, further including a pluralityof coils that are formed essentially in identical fashion.
 31. Thesemiconductor memory device of claim 23, further including two axiallysymmetrical coils with axes of symmetry and wherein the two coils arearranged with their axes of symmetry running on a common axis.
 32. Thesemiconductor memory device of claim 31, wherein the two coils arearranged along their common axis in a manner spaced apart spatially withan intermediate region, and wherein a semiconductor module underlyingthe semiconductor memory device is arranged at least partly in theintermediate region between the coils in particular in the vicinity ofthe common axis.
 33. The semiconductor memory device of claim 21,wherein the memory cells each have a magnetoresistive memory element, inparticular a TMR stack element with at least one hard-magnetic layer.34. The semiconductor memory device of claim 33, wherein the memorycells each have at least one soft-magnetic layer as memory layer andalso a tunnel layer arranged between the hard-magnetic layer and thesoft-magnetic layer.
 35. The semiconductor memory device of claims 34,wherein the hard-magnetic layer is in each case formed with a predefinedmagnetization as desired magnetization, which is in each case orientedperpendicularly to a course direction of the TMR stacked element orelements.
 36. The semiconductor memory device of claim 21, wherein theplurality of memory cells is formed essentially in identical fashion.37. The semiconductor memory device of claim 21, wherein the pluralityof memory cells is arranged or formed in such a way that theirmagnetizations are oriented to lie essentially in one plane.
 38. Amethod for operating a semiconductor memory device based on amagnetoresistive storage mechanism comprising: reading and externallystoring memory contents of each memory cell of a memory area of thesemiconductor memory device; applying a magnetic field to thesemiconductor memory device and applying the magnetic field to at leastsome of the memory cells in order to impress a magnetization onhard-magnetic layers of the memory cells in a definable and controllablefashion; and writing-back the externally stored memory contents to therespective cells of the memory area.
 39. The method of claim 38, whereinthe magnetic field is set in a controlled fashion in terms of itsstrength, orientation and time duration in such a way that each memorycell to be acted on has impressed on it a magnetization in a definedfashion in terms of strength and orientation such that a reliable memoryoperation is ensured, and that, in particular, the respectivemagnetization of hard-magnetic layers of the memory cells is reorientedtoward the desired magnetization (Mdesired) and amplified.
 40. Themethod of claim 38, wherein steps reading memory contents, applying amagnetic field and writing-back memory contents are carried out in amanner repeated at regular time intervals, and in particular at a timeinterval of one year or less and upon explicit request by a user.
 41. Amagnetoresistive semiconductor memory device comprising: a memory areahaving a plurality of memory cells; and means for applying a locallyhomogeneous magnetic field to at least some of the memory cells in acontrollable manner such that at least regions of the memory cells canbe oriented in a controllable manner with respect to theirmagnetization.
 42. The magnetoresistive semiconductor memory device ofclaim 41, wherein the magnetic field is impressed upon hard magneticlayers of the memory cells.